The present invention relates to semiconductor memory devices; and, more particularly, to semiconductor memory devices that measure the offset voltage of sense amplifiers.
In a semiconductor memory device such as a dynamic random access memory (DRAM), a bit line sense amplifier (hereinafter, “amp”) is used to amplify a low voltage level of data stored in each memory cell so that the data can be read outside the memory device.
FIG. 1 shows a data read path and a data write path in a core region of a conventional semiconductor memory device.
As shown, the memory device includes a cell array 510, a bit line sense amp block 520, a bit line sense amp (BLSA) controller 620, a word line driver 610, an IO sense amp 594, a write driver 592, a local I/O line precharger 570, and a Y decoder 630.
The semiconductor memory device further includes a bit line controller 650 for BLSA controller 620, a local precharger controller 530 for local I/O line precharger 570, a write driver controller 580 for write driver 592, and a Y decoder controller 640 for Y decoder 630.
In the conventional memory device, during a write operation, data from an input/output pad DQ is delivered to write driver 592 through a global input/output line GIO via an I/O driver 598. During a read operation, data stored in the cell array is forwarded to I/O driver 598 along global input/output line GIO through an IO sense amp 594 and then outputted through input/output pad DQ.
Write driver 592 and I/O sense amp 594 are coupled to bit line sense amp block 520 through local input/output lines LIO and LIOB, wherein a control signal Yi controls the connection. Y decoder 630 issues the control signal based on an inputted column address. Further, local I/O line precharger 570 precharges the local input/output lines LIO and LIOB.
Details of data processes from cell array to the bit line sense amp block in the semiconductor memory device, i.e., details of data processes in the semiconductor memory devices, such as sensing, amplifying, inputting, etc. are omitted herein because they are obvious to those skilled in the art.
Several specific circuits constitute BLSA controller 620, which activates sense amp 522; for example, where FIG. 2A shows a bit line selector 622, FIG. 2B depicts a bit line precharger controller 624, and FIG. 2C shows a sense amp driver 626.
In outputs from bit line sense amp 522, offset voltages may occur for various reasons, for example, a threshold voltage difference of MOS transistor devices, a difference in transconductance, a capacitance difference between a bit line and an inversion bit line, etc. Since voltage variation of the bit line is not large when data stored in cell array 510 is loaded, stable read operations in the semiconductor memory device are difficult to guarantee if the offset voltage of sense amp 522 is large. Thus, in order to secure a stable read operation in the semiconductor memory device, the offset voltage of the sense amp should be measured.
To measure the offset voltage of the sense amp according to prior art, a variation of the bias voltage of an electrode positioned opposite a cell storage node is specified. Then, the sense amp senses a data outputted from the cell array according to the variation of the bias voltage and, as a result, determines whether the data is erroneous, thereby computing offset voltage by applying a theoretical formula thereto.
In the conventional method, however, it is troublesome to precisely measure the capacitance of a unit cell in the cell array and the capacitance of the bit line coupled to the unit cell. Calculation of the pure offset voltage of the bit line sense amp has been difficult and until now, this voltage has been approximately calculated rather than actually measured. Stable operation of a semiconductor memory device cannot be guaranteed unless the offset voltage is correct.